Technical Field
The present invention relates to a wiring substrate and an electronic component device.
Related Art
In the related art, a semiconductor device in which a plurality of semiconductor chips is accommodated in one package in association with high performance and high functionality of an electronic device has been known. In an example of the semiconductor device, semiconductor chips are flip chip-connected to both surfaces of a single wiring layer, and the semiconductor chips on both the surfaces are sealed by a mold resin. Also, a terminal part of the wiring layer is exposed from a side surface or a lower surface of the mold resin.
Patent Document 1: JP-A-2001-358285
Patent Document 2: JP-A-2003-163325
Patent Document 3: JP-A-2007-335464
Patent Document 4: JP-A-2016-115870
As described later in paragraphs of preliminary matters, there is a semiconductor device having a structure where semiconductor chips are connected with being sealed by a resin to both surfaces of a single wiring layer and a wiring portion in an outer region of the semiconductor chip is bent downward.
In this semiconductor device, since the single wiring layer is used, a degree of freedom of wiring routing is low, so that it is difficult to cope with mounting of the high-performance semiconductor chip having various pad layouts.
As the measures against the above problem, if the wiring layer is configured by a multi-layered wiring layer, the multi-layered wiring layer is also bent at the same time. For this reason, a cured interlayer resin layer of the multi-layered wiring layer may be damaged, so that it is not possible to secure the reliability of the multi-layered wiring layer.